1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor integrated circuit device with a p-type MOSFET and an n-type MOSFET.
2. Description of the Related Art
In semiconductor integrated circuit devices, miniaturization of wiring is a continuing trend in increasing the integration level, and currently manufactured semiconductor integrated circuit devices include miniaturized MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with the gate length of 0.03 μm and fabricated with 0.065-μm wiring rules.
In a DRAM (Dynamic Random Access Memory), since a gate electrode is used as a wiring line, the width of the gate wiring line has the same dimension as the gate length. Therefore, reduced gate wiring resistance is necessary to satisfy both reduced voltage and increased operation speed of the DRAM. As conventional polycide wiring increases gate wiring resistance, a gate structure having a polymetal structure (hereinafter referred to as “polymetal gate”) is under research and development.
Since a polymetal gate has a structure in which a refractory metal is stacked on a polysilicon film and has a low sheet resistance of about 2 Ω/□, it can be used not only as a gate electrode but also as a wiring line. Examples of refractory metal to be used includes W (tungsten) and Mo (molybdenum) that show excellent low resistivity even after a low-temperature process is carried out at 800° C. or lower as well as high tolerance to electromigration. Stacking such a refractory metal film directly on a polysilicon film may reduce adhesivity therebetween and may form a high-resistance silicide layer at the interface therebetween in a high-temperature thermal treatment process. Therefore, an actual polymetal gate has a three-layer structure in which a barrier layer formed of a metal nitride film, such as tungsten nitride (WNx), is sandwiched between the polysilicon film and the refractory metal film.
The polysilicon film that forms part of the polymetal gate is doped with an impurity to reduce resistance of the polysilicon film. Directly forming the tungsten nitride film on the impurity-doped polysilicon film using PVD (Physical Vapor Deposition), such as sputtering, may increase resistance at the interface between the impurity-doped polysilicon film and the tungsten nitride film. To prevent the increase in interface resistance, in some cases, a silicide layer (WSi2) as a buffer layer is formed between the impurity-doped polysilicon film and the tungsten nitride film.
On the other hand, doping an impurity into the polysilicon film has typically been carried out using a method called an NN gate process for doping phosphorus as an impurity into the polysilicon for the gates of the N-type and P-type MOSFETs.
However, for higher-speed DRAMs, it has been essential to use a method called a PN dual gate process for doping N-type and P-type impurities into the polysilicon for the gates of N-type and P-type MOSFETs, respectively, as disclosed in Japanese Patent Laid-Open No. 2005-229130, for example.
The PN dual gate process will be described in detail with reference to diagrammatic process sectional-views of FIGS. 1 and 2.
Firstly, a silicon substrate 10 is thermally oxidized to form a gate oxide film 9 with a film thickness of 3 to 6 nm. Subsequently, a non-doped polysilicon film 1 with a film thickness of 70 nm is formed on the gate oxide film (FIG. 1(a)).
Thereafter, a photoresist film 7 is formed and typical photolithography is used to remove the photoresist film 7 from an N-type gate region 6(a), where an N-type MOSFET is later formed. Then, only the N-type gate region 6(a) is implanted with P (phosphorous) ions at an acceleration voltage of 10 keV and a dose of 6.0×1015 ions/cm2 by ion implantation to convert the non-doped polysilicon film 1 in the N-type gate region 6(a) into an N-doped polysilicon 8(a) doped with the N-type impurity (FIG. 1(b)).
Similarly, a photoresist film 7 is formed and typical photolithography is used to remove the photoresist film 7 from the P-type gate region 6(b), where a P-type MOSFET is later formed. Then, only the P-type gate region 6(b) is implanted with B (boron) ions at an acceleration voltage of 5 keV and a dose of 2.5×1015 ions/cm2 by ion implantation to convert the non-doped polysilicon film 1 in the P-type gate region 6(b) into a P-doped polysilicon 8(b) doped with the P-type impurity (FIG. 1(c)).
On the N-doped polysilicon 8(a) doped with the N-type impurity and the P-doped polysilicon 8(b) doped with the P-type impurity is formed a 5-nm tungsten silicide (WSi2) film 2 by CVD as a buffer layer for preventing increase in interface resistance. Then, thermal treatment is carried out at about 800° C. for about 30 seconds in a nitrogen atmosphere (FIG. 2). This thermal treatment serves both to activate the P (phosphorous) ions implanted in the N-type gate region 6(a) and the B (boron) ions implanted in the P-type gate region 6(b), as well as to remove residual impurities contained in the CVD raw material gas.
The tungsten silicide film formed may be alternatively formed, not by CVD, but by forming a tungsten (W) film on the N-doped polysilicon 8(a) and P-doped polysilicon 8(b) through sputtering and performing thermal treatment to induce reaction between the polysilicon and tungsten.
Then, on the tungsten silicide film 2 is formed a tungsten nitride film as a barrier layer, on which a tungsten film is formed. The resulting stacked film is processed into a desired pattern to form a gate electrode.
When the PN dual gate process is used to manufacture a semiconductor device as described above, variation in threshold value (Vt) may occur.
This variation in Vt is considered to be attributable to the following: In the polysilicon film, P (phosphorous), As (arsenic) or the like is implanted into the N-gate region as an N-type impurity while B (boron) or the like is implanted into the P-gate region as a P-type impurity. These impurities interdiffuse in the thermal treatment process to change the concentrations of the impurities. The Fermi position of the gate changes accordingly and hence the work function difference between the gate and the silicon substrate changes, resulting in the variation in Vt.
The mechanism of interdiffusion between the N-type and P-type impurities will be described with reference to FIG. 3.
The P-type impurity in the P-doped polysilicon film 8(b) in the P-type gate region 6(b) may diffuse into the N-doped polysilicon film 8(a) in the N-type gate region 6(a) through a path 11(a) in the tungsten silicide film 2, while the N-type impurity in the N-doped polysilicon film 8(a) in the N-type gate region 6(a) may diffuse into the P-doped polysilicon film 8(b) in the P-type gate region 6(b) through a path 11(b) in the tungsten silicide film 2, conceivably resulting in interdiffusion between the P-type and N-type impurities.
In such interdiffusion, impurities having opposite conductivity types diffuse into the counterpart regions, so that impurity concentrations vary in the polysilicon film and the work functions change accordingly, resulting in the variation in Vt.